This invention relates to a method of designing a semiconductor integrated circuit, and, in particular, to a method of verifying reliability of the semiconductor integrated circuit.
In a semiconductor integrated circuit, a delay time is caused to occur in an electronic circuit when the electronic circuit includes MOS (Metal Oxide Semiconductor) transistors. Recent years, MOS transistors tend to become very small in size. This makes it impossible to ignore an influence from a hot carrier effect. Moreover, the delay time is also varied by an influence of aging caused by the hot carrier effect.
In a conventional calculation method of the aged delay time, a difference, namely, a degradation rate between delay times before and after aging is calculated from information (input pin information) concerned with each input pin of a logic block and information (input pin device information) concerned with a device connected to the input pin. Hereinafter, the difference or a degradation rate will be called an delay time degradation rate. And then, the aged delay time is calculated from the delay time degradation rate.
Herein, input pin information concerned with rounding and a frequency of waveform inputted to a logic block is provided from a logic level circuit formed by the logic blocks. On the other hand, input pin device information is provided from devices inside of a logic block.
The conventional calculation method will be described in detail with reference to FIG. 1 and is specified by a delay time calculation method depicted by 100. The delay time calculation method is for calculating aged delay time of a logic level circuit. In this method, delay time degradation rate calculation 105 is executed to calculate the aging degradation amount or rate which occurs in one logic block. Such the delay time degradation rate calculation 105 is carried out on the basis of input pin information 102, passage time information 103 and input pin device information 104. The calculation 105 is iterated to all of logic blocks comprising a logic level circuit. From the result of repeated calculation 105, aged delay time calculation 106 is executed and finally, a calculation result 107 is gained.
As mentioned above, in the conventional method of calculating aged delay time of a logic level circuit, the aged delay time of each logic blocks is based only on the input pin information and then the result is applied for a calculation of aged delay time of whole of the logic level circuit. In this method, the accuracy of the aged delay time is low except that each logic block is composed of an inverter of one-stage transistor gate.
In another conventional method, the aged delay time can be obtained with a high accuracy. However, to accomplish such a high accuracy, each of the logic blocks should be separated into a great number of transistor gates to calculate rounding and a frequency of waveform through each transistor gate, instead of calculating the aging degradation amount at each logic block. Specifically, the calculation of aged delay time should be executed each of all transistors included in a logic level circuit. In short, high accuracy and a small amount of calculation have a tradeoff relationship in these methods.